FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a built-in test circuit, and particularly to a semiconductor integrated circuit having a test circuit for screening mass-produced goods. Description of the Related Art
The maximum value of the operating frequency of a semiconductor integrated circuit (hereinafter referred to as an IC) is generally determined by each transistor's switching speed, which is a constituent element of the IC, this switching speed depending on such factors as the gate length and the transistor logic threshold value generated by a diffusion process. When developing an IC, sufficient rating for a market product is carried out by using several test products as samples which are tested by being subjected to various conditions of use. Inevitably, even with products that have been sufficiently rated, there will be some products among completed articles that do not deliver the expected performance due to variations in raw materials and manufacturing conditions. As a result, various screening tests are carried out before shipment to prevent the shipment ment of defective products.
The measurement of maximum operating frequency is included among these tests. This test involves impressing a power source voltage set as the used standard to an IC to which is inputted a driving clock pulse from the outside, and testing whether or not the IC operates normally at the standard clock frequency. A concrete maximum operation frequency measurement uses an LSI tester in which the frequency driving the IC is set to a value higher than for standard use, inputting random test pattern data, and comparing the values outputted by the IC with expected values for each test cycle. If the resulting IC output values match the expected values, the IC is judged to be a product capable of meeting the use standards guaranteed to a user. If the values do not match, the IC is judged to be defective.
FIG. 1A is a timing chart for carrying out such a test, the relation of the clock pulse high width and the clock pulse low width to the clock time width T is normally T/2 for each. An increase in clock frequency means that the clock time width T will be reduced, and accordingly, the time width 1/2 T of the clock pulse high and clock pulse low, which are each 1/2 of the clock pulse time width, will also be reduced.
The performance of the above-described LSI tester will also improve along with the improvement of the performance of the tested IC. In particular, for measuring the performance of an IC in which the use standard for maximum operating frequency is set high, an LSI tester must have high-level performance , and in particular, must be capable of measuring high frequency, and for this purpose, high-performance, high-speed LSI testers have been developed. However, such high-performance LSI testers are extremely expensive, and while a few units may be used for research and development, installation of the large number of LSI testers necessary for use in screening during mass 10 production would entail a huge investment in equipment and would result in an increase in IC manufacturing costs.
As a result, a conventional method of measurement in mass production screening employs normal IC testers of lower frequency that indirectly test the maximum operating frequency of an IC by setting the widths of only the clock pulse high and low alternately to less than 1/2 the clock time width of the maximum operating frequency of the use standard, inputting random test patterns to the IC, and comparing the outputted values of the IC with the expected values for each test cycle. In this case, if the outputted values and the expected values match for the time width of both the high and the low even when reduced, the IC is judged to meet the standards for maximum operating frequency, and if the values do not match, the IC is judged to be defective. A timing chart for this case is shown in FIG. 1B. In FIG. 1B, the clock time width T is the time width during which the IC can operate normally, the width of the clock pulse high and the width of the clock pulse low are alternately reduced to less than 1/2 the width of the maximum operating frequency and tested, and the IC meets the standards if the results of both are satisfactory.
However, setting each of the high width and the low width of the clock pulse to a reduced value and testing each IC twice leads to a lengthy test time and an increase in both screening and production costs, and prevents the provision of low-cost ICs to users.